A computer system may be divided into three basic blocks: a central processing unit (CPU), memory, and input/output (I/O) units. These blocks are coupled to each other by a bus. An input device, such as a keyboard, mouse, disk drive, analog-to-digital converter, etc., is used to input instructions and data to the computer system via an I/O unit. These instructions and data can be stored in memory. The CPU retrieves the data stored in the memory and processes the data as directed by a set of instructions. The results can be stored back into memory or outputted via an I/O unit to an output device such as a printer, cathode-ray-tube (CRT) display, digital-to-analog converter, etc.
Data is stored back into memory as a result of the computer system performing a store operation. In the prior art, a store operation included an address calculation and a data calculation. The address calculation generated the address in memory at which the data is going to be stored. The data calculation produces the data that is going to be stored at the address generated in the address calculation portion of the store operation. These two calculations are performed by different hardware in the computer system and require different resources. In the prior art, the store operation is performed in response to one instruction, or one part of an instruction, wherein the data calculation is performed first and, once complete, the address calculation occurs as the operation goes to memory for execution.
When a store operation is dispatched to memory, the processor must allocate time to dispatch the store as soon as the store is ready to be dispatched. Therefore, the store operation demands immediate attention from the processor that might be directed to other operations or functions. However, often there is no other immediate requirement that the store be completed. Thus, it is desirable to allow store operations to be dispatched separately from the processor and the remaining operations its performing.
The present invention provides for performing of store operations such that the store operations are designated to memory and committed to system state. In this manner, the store operations are dispatched at the convenience of the memory system.